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PRELIMINARY
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
INTRODUCTION
48-LQFP-0707 S5L9290X is a signal processing LSI for the CD. Digital processing function (EFM demodulation, error correction), spindle motor servo processing, wide capture range DPLL and 1-bit DAC for the CD player are installed in S5L9290X.
FEATURES
* Signal processing part -- EFM data demodulation -- Frame sync detection, protection, insertion -- Sub code data processing (Q data CRC check, Q data register installed) -- Error correction (C1: 2 error correction, C2: 4 erasure correction) -- Installed 16K SRAM for De-interleave -- Interpolation -- Digital audio interface -- CLV servo control (X1, X2) -- Wide capture range digital PLL ( 50%) * Digital filter, DAC part -- 4 times over sampling digital filter -- Digital de-emphasis (can be process the 32kHz, 44.1kHz, 48kHz) -- Sigma-delta stereo DAC installed -- Audio L.P.F installed
ORDERING INFORMATION
Device S5L9290X01L0R0 Package 48-LQFP-0707 Supply Voltage 2.7V 3.3V (Analog, Internal logic) 2.7V 5.5V (I/O port) Operating Temperature -20C +75C
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PRELIMINARY
S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
BLOCK DIAGRAM
SQCK SBCK
SOS1 SQDT SBDT
C2PO
DATX
VCO1LF EFMI DPLL
Subcode Out
Digital Out
LOCK SMEF SMDP SMDS WDCK
EFM Demodulator
Interpolator
Digital Filter
CLV Servo
ECC
1-bit DAC
WFCK RFCK C4M XIN ISTAT MLT MDAT MCK MUTE
Timing Generator
16K SRAM PWM
Micom Interface
Address Generator
I/O Interface
LPF
JITB
SADTO LRCKO BCKO
SADTI LRCKI BCKI
LCHOUT VHALF RCHOUT VREF
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PRELIMINARY
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
PIN CONFIGURATION
VDDD_DAC
VDDA_DAC
VSSD_DAC
VSSA_DAC
VDDA_PLL
RCHOUT
LRHOUT
VHALF
SADTI
LRCKI 38
VREF
48 VSSA_PLL VCO1LF 1 2
47
46
45
44
43
42
41
40
39
37 36 BCKO 35 LRCKO 34 SADTO 33 DATX 32 C2PO
VSSD_PLL 3 VDDD_PLL 4 VDDD1_5V 5 XIN XOUT 6 7
S5L9290X
DSP+DAC
48-LQFP-0707
BCKI
31 JITB 30 SBCK 29 VDDD3-5V 28 VSSD2-3V 27 VDDD2-3V 26 MUTE 25 SQDT
VSSD1_5V 8 EFMI 9
LOCK 10 SMEF 11 SMON 12
13 SMDS
14 WDCK
15 TESTV
16 LKFS
17 LKFS
18 RESETB
19 MLT
20 MDAT
21 MCK
22 ISTAT
23 S0S1
24 SQCK
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PRELIMINARY
S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
PIN DESCRIPTION
Table 1. Pin Description NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NAME VSSA_PLL VCO1LF VSSD_PLL VDDD_PLL VDDD1-5V XIN XOUT VSSD1 EFMI LOCK SMEF SMDP SMDS WDCK TESTV LKFS C4M RESETB MLT MDAT MCK ISTAT S0S1 SQCK I/O O I O I O O O O O I O O I I I I O O I Analog Ground for DPLL Pump out for VCO1 Digital Ground Separated Bulk Bias for DPLL Digital Power Separated Bulk Bias for DPLL (3V Power) Digital Power (5V Power, I/O PAD) X'tal oscillator input (16.9344MHz) X'tal oscillator output Digital Ground (I/O PAD) EFM signal input CLV Servo locking status output LPF time constant control of the spindle servo error signal Phase control output for Spindle Motor drive Speed control output for Spindle Motor drive Word clock output (Normal Speed : 88.2KHz, Double Speed : 176.4KHz) Various Data/Clock Input The Lock status output of frame sync 4.2336MHz clock output System Reset at 'L' Latch signal input from Micom Serial data input from Micom Serial data receiving clock input from Micom The internal status output to Micom Subcode sync signal(S0+S1) output Subcode-Q data transfering bit clock input Pin Description
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PRELIMINARY
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
Table 1. Pin Description (continued) NO. 25 26 27 28 28 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NAME SQDT MUTE VDDD2-3V VSSD2 VDDD3-5V SBCK JITB C2PO DATX SADTO LRCKO BCKO BCKI LRCKI SADTI VSSD_DAC VDDD_DAC RCHOUT VSSA_DAC VREF VHALF VDDA_DAC LCHOUT VDDA_PLL I/O O I I O O O O O O I I I O O O O Function Description Subcode-Q data serial output System mute at 'H' Digital Power (3V Power, Internal Logic) Digital Ground (Internal Logic) Digital Power (5V Power, I/O PAD) Subcode data transfering bit clock Internal SRAM jitter margin status output C2 pointer output Digital audio data output Serial audio data output (48 slot, MSB first) Channel clock output Bit clock output Bit clock input Channel clock input Serial audio data input (48 slot, MSB first) Digital Ground for DAC Digital Power for DAC (3V Power) Right-Channel audio output through DAC Analog Ground for DAC Referance Voltage output for bypass Referance Voltage output for bypass Analog Power for DAC (3V Power) Left-Channel audio output through DAC Analog Power for PLL (3V Power)
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PRELIMINARY
S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
MAXIMUM ABSOLUTE RATINGS
Item Power supply voltage Input supply voltage Operating temperature Storage temperature Symbol VDD VI TOPR TSTG Rating 3V: -0.3 3.8 5V: -0.3 7.0 3V I/O: -0.3 VDD + 0.3 5V I/O: -0.3 5.5 -20 75 -40 125 Unit V V C C
ELECTRICAL CHARACTERISTICS
OPERATING CONDITION
Item Power supply voltage
Symbol VDD TOPR
Operating Range 3V: 2.7 3.3 5V: 4.5 5.5 -20 75
Unit V C
Operating temp.
DC CHARACTERISTIC (VDD = 3.0V, VSS = 0V, TA = 25C)
Design Values Item 'H' input voltage 'L' input voltage 'H' output voltage 'L' output voltage Input leak current Three state output leak current Symbol VIH VIL VOH(1) VOL(1) ILKG IOZ IOH = -1mA IOL = 1mA VI = 0-VDD VO = 0-VDD Condition Min 0.8VDD VDD-0.2 -10 -10 Typ Max 0.2VDD 0.4 10 10 Unit V V V V uA uA (Note 2) (Note 3) (Note 4) (Note 1) Comment
NOTES: 1. Related pins: All input terminal 2. Related pins: All output terminal 3. Related pins: All input terminal 4. Related pins: SMEF, SMDP, SMDS, ISTAT
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PRELIMINARY
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
AC CHARACTERISTIC When Pulse is Applied to XIN (Ta = 25C, VDD = 3.0V, VSS = 0V) Item 'H' level pulse width 'L' level pulse width Pulse frequency Input 'H' level Input 'L' level Rising & falling time Symbol TWH TWL TCK VIH VIL TR,TF Min 13 13 26 VDD-1.0 Typ Max 0.8 10 Unit ns ns ns V V ns
TCK TWH TWL VIH_max VIH_max*0.9 VDD/2 VIL_max*0.1 VIL_min TR TF
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PRELIMINARY
S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
MCK, MDAT, MLT (Ta = 25C, VDD = 3.0V, VSS = 0V) Item Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width SQCK frequency SQCK pulse width Symbol FCK1 TWCK1 TSU TH TD TW FCK2 TWCK2 Max 1 1 Typ Min 500 300 300 300 1000 500 Unit MHz ns ns ns ns ns MHz ns
1/FCK1 TWCK1 TWCK1 MCK MDAT MLT SBCK SQCK TSU TH TD TW
TWCK2
TWCK2
1/FCK2 SQDT SBDT
TSU TH
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PRELIMINARY
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
DESCRIPTION OF OPERATION
MICOM INTERFACE Each command is executed when data and command is input as LSB first according to timing shown in the figure below through MDAT, MCK, and MLT inputs and ISTAT output. * * Address: 8 bit Data: 8 bit (writing), 8/16 bit (reading)
MDAT MCK MLT Register
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 D11 D12 D13 D14 D15
[MSB]
valid
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PRELIMINARY
S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
DSP Command
Data Command DPLL control 1 DPLL control 2 DPLL control 3 DPLL control 4 DPLL control 5 Address D7 10001000 ($88) 10001001 ($89) 10001010 ($8A) 10001100 ($8C) 1000101 ($8D) CMD SPLIT PHASE ONLY FDEEM ZCMT WIDE D6 PHSE DET D5 PHASE GAIN D4 DLF GAIN D3 ACC3t MAXTGAIN[1:0] DIVP1 [1:0] DIVM1[7:0] MRANGE[1:0] DEEM ZDENL ERA OFF ATTN FSREG C1PNT DAC MUTE PLL TEST VFLGC PLL PWDN1 DATX MUTE NCLV WP CM1 JITM DATX OENB CRCQ JTFRV1 GAIN CM0 D2 D1 CO3T D0 RETRE F
ISTAT pin Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z EMPH S0S1 LKFS JITB LOCK EFMFLA G /(PW64) Hi-Z Hi-Z Hi-Z
REF98[1:0] DIVS1 [1:0]
REF98[1:0]
CAPRANGE [1:0]
Function control 10010000 CDROM ($90) Audio control Frame Sync control Mode control 1 Mode control 2 CLV gain control CLV mode control CLV control 1 CLV control 2 CLV control 3 CLV control 4 CLV control 5 CLV control 6 10010001 ($91) 10010010 ($92) 10010011 ($93) 10010100 ($94) 10011000 ($98) 10011001 ($99) 10011010 ($9A) 10011011 ($9B) 10011100 ($9C) 10011101 ($9D) 10011110 ($9E) 10011111 ($9F) SMEF OUTB SPLUS MUTE
FSEL [1:0] GNR PWDN MSCK SW OVSPL WBN
WSEL[1:0] DAC PWDNB WPN CLV IDLE PME PCEN SME
FSMD [1:0] ECLV RFCK SW OVSPL MS CM3 ECLV PD WB CM2
UNLOCK[1:0] STRIO LC SMM PML
PCKSEL[1:0] POS
PGAIN[1:0] SGAIN[2:0]
SML[1:0]
POFFSET[7:0] SDD PHASEDIV[1:0] SOFFSET[7:0] CLV DEFT DSVEN DSV3T DSVINV DSVGAIN[1:0] SMOFFSET[3:0]
Hi-Z Hi-Z Hi-Z
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PRELIMINARY
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
Data Command 1-bit DAC & DATX control 1-bit DAC attenuation control Output port control SADT I/F control Play mode control TEST mode control Address D7 10100011 ($A3) 10100100 ($A4) 10101001 ($A9) 10110000 ($B0) 11110000 ($F0) 11111111 ($FF) DS1 M5 D6 D5 D4 D3 SC[3:0] M2 M1 M0 D2 D1 D0 TXSF [3:0] M4 M3 SPLFREQ[1:0] SOFT ATTN CMD DIRECT MSON -
ISTAT pin Hi-Z Hi-Z
TALK [3:0] DS0 -
-
DFCK -
Hi-Z Hi-Z Hi-Z Hi-Z
TEST [3:0]
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PRELIMINARY
S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
$88 Command Digital PLL control
Data Command Address D7 DPLL control 1 10001000 ($88) WIDE D6 PHASE DET D5 PHASE GAIN D4 DLF GAIN D3 ACC3t D2 D1 CO3T D0 RETREF
Bit D7 D6 D5 D4 D3 D2 D1 D0 $89 Command Digital PLL control
Name WIDE PHASE-DET PHASE-GAIN DLF-GAIN ACC3t CO3T REFRET
Data = 0 Normal Now 1/2t 1/2^10 ignore 3t Normal 1.1%
Data = 1 Wide new 1t 1/2^9 accept 3t 3T 2.3%
Comment Wide mode selection Phase detection method selection (option) Phase Adjust gain selection (option) Digital loop filter gain selection (option) ROM coefficient selection (option) 3T correction (option) Reference when return to M1 = 98
Data Command Address D7 DPLL control 2 10001001 ($89) D6 D5 REF[1:0] D4 D3 D2 D1 D0
REF98[1:0]
MAXTGAIN[1:0]
CAPRANGE[1:0]
Bits D[7:6] D[5:4] D[3:2] D[1:0]
Name REF98[1:0] REF[1:0] MAXTGAIN[1:0] CAPRANGE[1:0]
Data = 00 1.7% 1.7% 1 50%
Data = 01 2.3% 2.3% 1/2 40%
Data = 10 3.4% 3.4% 1/4 30%
Data = 11 4.6% 4.6% 1/8 20%
Comment Outward reference when M1 = 98 Outward reference when M1 98 MAX T accumulation gain Capture range selection
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PRELIMINARY
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
$8A Command Digital PLL control
Data Command Address D7 DPLL control 3 10001010 ($8A) D6 D5
D4
D3
D2
D1
D0
DIVS1[1:0]
DIVP1[5:0]
Bits D[7:6]
Name DIVS1[1:0]
Data = 00 1
Data = 01 1/2
Data = 10 1/4
Data = 11 1/8
Comment PLL1 post scalar
Bits D[5:0]
Name DIVP1[5:0]
Data = 000000 - 111111 0 - 63
Comment PLL1 pre divider
$8C Command Digital PLL Control
Data Command Address D7 DPLL control 4 10001100 ($8C) D6 D5 D4 D3 D2 D1 D0
DIVM1[7:0]
Bits D[7:0]
Name DIVM1[7:0]
Data = 00000000 - 11111111 0 - 255
Comment PLL1 main divider
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PRELIMINARY
S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
$8D Command Digital PLL control
Data Command Address D7 DPLL control 5 10001101 ($8D) CMD SPLIT D6 PHASE ONLY D5 D4 D3 FSREG D2 PLLTEST D1 PLL PWRDN1 D0 -
MRANGE[1:0]
CMD_SPLIT (option) The digital PLL control micom command is automatically applied when the speed is changed($F0) or at Jitter Free2($94). H : Each DPLL control Micom Commands ($8A, $8B, $8B) are applied using the Micom Interface terminals (MCK, MDAT, MLT). L : DPLL control Micom Command ($8A, $8B, $8B) is applied automatically inside. PHASE_ONLY (option) Controls phase compensation status at DPLL. H : Phase compensation L : Phase compensation + Frequency compensation MRANGE[1:0] Controls the range of the PLL1 Main Divider M value range
Bits D[5:4] Name MRANGE[1:0] Data = 00 50% Data = 01 40% Data = 10 30% Data = 11 20% Comment Lock Range
FSREG Verifies the Frame Sync status(|Thigh-Tlow| 1) at MAX T H : Verify L : Ignore PLLTEST PLL1 TEST mode H : TEST (M1<=M2), PLL PWDN1 PLL1 Power Down mode H : Power Down,
L : Normal
L : Normal
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PRELIMINARY
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
$90 Command DSP Function Control
Data Command Address D7 Function control 10010000 ($90) CDROM D6 FDEEM D5 DEEM D4 ERA OFF D3 C1PNT D2 D1 D0 JITM
CDROM H: CDROM mode L: CDP mode FDEEM, DEEM De-Emphasis Automatic control and compulsion control select FDEEM 0 0 1 1 DEEM 0 1 0 1 De-emphasis on/off Off On/Off Off On Comment Automatic operate to detect emphasis signal of subcode information Operate without regard to emphasis signal of subcode information
ERA_OFF: H: Erasure correction off L: Erasure correction on C1PNT : C1 2 Error correction C1 pointer set/reset control H: C1PNT = reset L: C1PNT = set C1PNT (option) Mute SRAM Address copy permission (Write base count copy from read base counter) H: Accept L: Reject
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PRELIMINARY
S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
$91 Command (Default value: 00000000) Control of each function related to audio data
Command Audio control Address 10010001 ($91) Data D7 MUTE D6 ZCMT D5 ZDENL D4 ATTN D3 DAC MUTEB D2 VFALG D1 DATX MUTE D0 DATX ENB
MUTE DSP MUTE enable signal H: DSP MUTE on L: DSP MUTE off ZCMT DSP Zero cross mute enable signal (effective when MUTE signal is ON) H: DSP Zero cross mute on L: DSP Zero cross mute off ZDENL 1-bit DAC Zero detection MUTE disable signal H: 1-bit DAC Zero detection MUTE off L: 1-bit DAC Zero detection MUTE on ATTN DSP -12dB attenuation enable signal H: DSP Attenuation on L: DSP Attenuation off DAC MUTEB Set the input data 1-bit DAC function block to 'L' H: DAC MUTE off. L: DAC MUTE on VFALG: Control the input V-bit to DATX Block H: 'L' set L: C2PO use DATX_MUTE: Set the input data to digital audio interface function block to 'L' H: DATX MUTE on L: DATX MUTE off DATX_ENB: DATX function disabled, fixed DATX output. H: DATX output disable L: DATX output enable ATTN 0 0 1 1 MUTE 0 1 0 1 dB 0 - - 12 - 12

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PRELIMINARY
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
$92 Command Control of functions related to frame sync
Data Command Frame sync control Address D7 10010010 ($92) D6 D5 D4 D3 D2 D1 D0 -
FSEL[1:0]
WSEL[1:0]
FSMD [1:0]
FSEL[1:0]:
Control of cycle for frame sync protection and insertion FSEL[1:0] 00 01 10 11 Control Cycle (Frame) 2 4 8 13
WSEL[1:0]: Control of window size related to frame sync protection WSEL[1:0] 00 01 10 11 FSMD: [1:0] Frame sync detection method control Detection Method Pattern Compensation Cycle 1 Cycle 2 11t 11t 11t 11t, 10 12t, 12t 10t 10t 11t, 11t 12t, 11t 11t, 11t 10t, 12t 11t cycle 1, 10t 12t, 12t 10t Comment Window Size(t) 3 7 13 26
FSMD [1:0] 00 01 10 11
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PRELIMINARY
S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
$93 Command Control of modes of functions in DSP
Command Address D7 Mode control 1 10010011 ($93) GNR PWRDN D6 D5 DAC PWPDNB D4 Data D3 ECLV D2 ECLV PD D1 NCLV D0 CRCQ
GNR_PWDN DSP Power Down H : Power Down On, L : Power Down Off DAC_PWDNB 1-bit DAC function Power Down H : Power Down Off, L : Power Down On ECLV Emergency CLV Servo, Overflow prevention H : Repeat output of H, Hi-Z, and L at a regular cycle through the SMDP terminal L : normal operation ECLV_PD SMDP output cycle control at ECLV H: Bottom Hold cycle (Refer to $98) L : Peak Hold cycle(Refer to $98 ) NCLV H : CLV phase servo driven by frame sync L : CLV phase servo driven by base counter CRCQ L : SQDT without SQOK H : SQDT with SQOK (If S0S1 is 'H', SQDT = SQOK)
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PRELIMINARY
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
$94 Command Control of function modes in DSP
Command Address D7 Mode control 2 10010100 ($94) MSCK SW D6 WDCK SW D5 D4 Data D3 RFCK SW D2 D1 D0 JTFRV1
Bit D7 D6 D5 D4 D3 D2 D1 D0
Name MSCK_SW WDCK_SW RFCK_SW JTFRV1
Data = 0 Internal X'tal MICOM X'tal
Data = 1 External VCO2 TESTV VCO1
jitter mode
Comment Input SBCK terminal when input the 1-bit DAC master clock in external WDCK frequency selection Use RFCK clock in CLV sero processing according to Use VCO1 clock in data processing
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PRELIMINARY
S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
$98 Command Control cycle and gain control in CLV speed mode
Data Command CLV gain control Address D7 10011000 ($98) OVSPL D6 WBN D5 WPN D4 D3 OVSPL MS D2 WB D1 WP D0 GAIN
OVSPL (option) Output by oversampling the CLV output (SMDP, SMDS) cycle by 7.35kHz *4 H : Over-sampling Enable, L : Over-sampling Disable WBN (option) Bottom Hold Cycle control in the CLV speed mode H : RFCK/64, L : determined by WB WPN (option) Peak Hold cycle control in the CLV speed mode H : RFCK/8, L : determined by WP OVSPL_MS (option) SMDS output mode setting at over-sampling enable H : PWM (H, L), L : Tri-State (H, Hi-Z, L) WB Bottom Hold cycle control in the CLV speed mode H : RFCK/16, L : RFCK/32 WP Peak Hold cycle control in the CLV speed mode H : RFCK/2, L : RFCK/4 GAIN SMDS output gain control in the CLV speed mode H : 0dB, L : -12dB
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PRELIMINARY
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
$99 Command CLV mode control
Data Command CLV mode control Address D7 10011001 ($99) D6 D5 CLV IDLE D4 PCEN D3 CM3 D2 CM2 D1 CM1 D0 CM0
UNLOCK [1:0]
UNLOCK[1:0] unlock cycle control UNLOCK[1:0] 00 01 10 11 Function If LKFS can remain at 'L' for 128 frames, the LOCK is 'L'. If LKFS can remain at 'L' for 112 frames, the LOCK is 'L'. If LKFS can remain at 'L' for 96 frames, the LOCK is 'L'. If LKFS can remain at 'L' for 80 frames, the LOCK is 'L'.
CLV_IDLE Use to place CLV servo control in idle mode. (Set POS ($9B) to 'H') H : Output a specific error ($9E, SOFFSET[7:0])to the SMDS terminal, IDLE mode. L : Normal Mode PCEN Phase Error Masking status determination when setting the dead zone. H : SMDP Phase Error Masking Enable. (When WFCK frequency Error has entered the Dead Zone) L : SMDP Phase Error Masking Disable. CM3 CM0 CLV Servo Control Mode Setting Mode Forward (KICK) Reverse (BRAKE) Speed (CLV-S) Phase (CLV-P) XPHSP (CLV-A) D3-D0 1000 1010 1110 1111 0110 SMDP H L Speed Phase Speed Phase SMDS Hi-Z Hi-Z Hi-Z Phase Hi-Z Phase SMEF L L L Hi-Z L Hi-Z SMON H H H H H Function Spindle motor forward mode Spindle motor reverse mode Rough servo mode at start up PLL servo mode Normal play mode (When LOCK is 'H', CLV-P operation and when 'L', CLV-S operation ) Automatic servo mode (When LOCK is 'H' or GFS is 'H', operate in CLV-P, but others, operate in CLVS') Spindle motor stop mode
VPHSP (CLV-A)
0101
Speed Phase L
Hi-Z Phase Hi-Z
L Hi-Z L
H
Stop (STOP)
0000
L
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PRELIMINARY
S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
$9A Command Digital CLV control
Data Command Address D7 CLV control 1 10011010 ($9A) STRIO D6 SMM D5 PME D4 SME D3 D2 D1 D0
PCKSEL[1:0]
PGAIN[1:0]
STRIO: Tri-state out enable in phase mode H: Tri-state L: PWM SMM: SMDS mask limit manual setting enable H: Manual setting L: Auto setting SMDP mask enable H: Mask enable L: Mask disable SMDS mask enable (dead zone enable) H: Mask enable L: Mask disable
PME:
SME
PCKSEL[1:0]: MDP resolution clock selection
Bits D[3:2]
Name PCKSEL [1:0]
Data = 00 CLK4M_CLV/2
Data = 01 CLK4M_CLV/4
Data = 10 CLK4M_CLV/8
Data = 11 CLK4M_CLV/ 16
Comment MDP resolution clock selection
PGAIN: SMDP gain setting
Bits D[1:0] Name PGAIN[1:0] Data = 00 1 Data = 01 1/2 Data = 10 1/4 Data = 11 1/8 Comment MDP gain selection
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PRELIMINARY
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
$9B Command Digital CLV control
Data Command Address D7 CLV control 2 10011011 ($9B) LC D6 PML D5 SML[1:0] D4 D3 POS D2 D1 SGAIN[2:0] D0
LC:
Lock control H : 1x 2x or 2x 1x then LOCK is forced to 0 L : Normal LOCK control MDP mask limit H : SMDP mask for SMDS error center value 50% L : SMDP mask for SMDS error center value 25% MDS mask limit (dead zone area) at MDS error error center value
Name SML[1:0] Data = 00 0% Data = 01 6.25% Data = 10 12.5% Data = 11 25% Comment Dead zone selection
PML :
SML:
Bits D[5:4]
When it enters the dead zone around the data rate, the MDS error value is output as 0. This minimizes the change in plus(+) and minus(-) frequently generated in the reference data rate and reduces the number of times required for motor control to reduce power consumption. The phase control also turns off in this dead zone. POS: MDP output selection H: Gain controlled SMDP L: Normal SMDP
SGAIN: SMDS gain setting SGAIN[2:0] 000 001 010 011 100 101 110 111 Gain Value 1 2 4 8 16 32 64 128
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S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
$9C Command Digital CLV control
Data Command Address D7 CLV control 3 10011100 ($9C) D6 D5 D4 D3 D2 D1 D0
POFFSET[7:0]
POFFSET[7]:SMDP offset sign H: Minus (-) L: Plus (+) POFFSET[6:0]: SMDP offset absolute value $9D Command Digital CLV control
Data Command Address D7 CLV control 4 10011101 ($9D) SPLUS D6 SDD D5 D4 D3 D2 D1 D0
PHASEDIV[1:0]
SMOFFSET[3:0]
SPLUS: SMDS offset plus enable H: Enable L: Disable SDD: SMDS speed down control disable H: Speed down control disable L: Speed down control enable
PHASEDIV[5:4]: Phase comparator period setting
Bits D[5:4] Name PHASEDIV[1:0] Data = 00 RFCK/2 Data = 01 RFCK/4 Data = 10 RFCK/8 Data = 11 RFCK/16 Comment Phase comparator period selection
SMOFFSET[3:0]:SMDS mask limit value 0000 - 1111
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PRELIMINARY
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
$9E Command Digital CLV control
Command CLV control 5 Address 10011110 ($9E) Data D7 D6 D5 D4 D3 D2 D1 D0
SOFFSET[7:0]
SOFFSET[7:0]: SMDS offset If SPLUS is 1, add SOFFSET to SMDS error to output the final error. $9F Command Digital CLV control
Command SBS Filter Gain Control 2 Address 10011111 ($A2) Data D7 SMEF OUTB D6 CLV DFCT D5 D4 DSVEN D3 DSV3T D2 DSVINV D1 D0
DSVGAIN[1:0]
SMEF_OUTB Control the SMEF output SMEF_OUTB 0 1 Speed mode Phase mode Speed mode Phase mode SMDP H, L, Hi-Z H, L, Hi-Z H, L, Hi-Z H, L, Hi-Z SMDS Hi-Z Hi-L Hi-Z Hi-L SMEF L Hi-Z Hi-Z L SMON H H H H
CLV_DFCT If the EFM pulse width is greater than 64T, it assumes a defect in the CLV servo control; makes SMDP and SMDS to Hi-Z; and stops the CLV servo control H: Defect detection control enable L: Defect detection control disable DSVEN DSV output enable signal H: DSV signal output in LKFS termianl L: DSV output disable (LKFS signal out) DSV3T Calculate only the 3T in EFM signal H: Only 3T DSVINV Invert output the DSV signal H: Invert output DSVGAIN [1:0] Decide the DSV output gain
Bits D[1:0] Name DSVGAIN[1:0] Data = 00 Data = 01 Data = 10 Data = 11 Comment
L: All T
L: Normal output
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PRELIMINARY
S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
$A3 Command 1-bit DAC Mode control
Data Command 1-bit DAC & DATX control Address D7 10100011 ($A3) D6 D5 D4 D3 SC[1:0] D2 D1 D0
TXSF[3:0]
SPLFREQ [1:0]
TXSF [3:0] DATX Sampling rate control Control the sampling rate (bit 24 - bit 27) among the control status data in digital audio output signal (DATX) TXSF [3:0] 0000 0100 1100 Others SC[1:0] Calibration range scale control Sampling rate 44.1kHz 48kHz 32kHz Reserved
Bits D[1:0]
Name SC[1:0]
Data = 00 X1
Data = 01 X2
Data = 10 X4
Data = 11 X0.5
Comment Effective when use the zero detection mute
SPLFEQ[1:0] Decide the 1-bit DAC Sampling frequency
Bits D[1:0]
Name SPKFREQ[1:0]
Data = 00 44
Data = 01 48
Data = 10 32
Data = 11 Reserved
Comment Audio data sampling frequency (kHz)
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PRELIMINARY
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
$A4 Command Digital attenuation level control
Command DAC ATTN control Address 01011101 ($5D) Data D7 M5 D6 M4 D5 M3 D4 M2 D3 M1 D2 M0 D1 SOFT ATTN D0 CMD DIRECT
M5 - M0 Attenuation level control (64 step)
MDAT MSB LSB M5 M4 M3 M2 M1 M0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Attenuation Level (dB) 0 -0.28 -0.42 -0.56 -0.71 -0.86 -1.01 -1.16 -1.32 -1.48 -1.64 -1.80 -1.97 -2.14 -2.32 -2.50 -2.68 -2.87 -3.06 -3.25 -3.45 -3.66 -3.87 -4.08 -4.30 -4.53 -4.76 -5.00 -5.24 -5.49 -5.75 -6.02 MDAT MSB LSB M5 M4 M3 M2 M1 M0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Attenuation Level (dB) -6.30 -6.58 -6.88 -7.18 -7.50 -7.82 -8.16 -8.52 -8.89 -9.28 -9.68 -10.10 -10.55 -11.02 -11.51 -12.04 -12.60 -13.20 -13.84 -14.54 -15.30 -16.12 -17.04 -18.06 -19.22 -20.56 -22.14 -24.08 -26.58 -30.10 -36.12 -
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PRELIMINARY
S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
SOFT ATTN Enable soft attenuation. The attenuation level is divided into 64 steps.
SOFT ATTN 23.2ms 0 dB set1 set2 set3 set4 dB < Soft Attenuation Operation >
8
set5
smoothly
directly set6
CMD DIRECT (option) L : Attenuate the 1-bit DAC using the soft attenuation block. H : Apply direct attenuation level to the 1-bit DAC without using the soft attenuation block. This disables the soft attenuation.
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PRELIMINARY
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
$A9 Command Output signal on/off control and monitor output selection
Data Command Output port control 2 Address D7 10101001 ($A9) D6 D5 D4 D3 D2 D1 D0 -
TALK[3:0]
TALK [3:0]: Monitoring Terminal output selection If MSON of $B0 is "H" state, SET TALK [2:0] = 0000
Bit Name TALK[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1XXX LKFS LKFS LKFS PLCK WFCK Fchange DIVN[5] LKFS LKFS LKFS C2PO C2PO C2PO C2PO C2PO DIVN98 DIVN[4] C2PO LKFS C2PO
Output Description JITB JITB ECFL3 FSYNC RFCK DIVNFAST DIVN[3] JITB JITB SBDT SADTO SADTO ECFL2 FSDW SQOK AT2T DIVN[2] DAC_SADT SADTO SADTO LRCKO LRCKO ECFL1 ULKFS TIM2 EFMIN DIVN[1] DAC_LRCK LRCKO LRCKO BCKO BCKO ECFL0 EFMFLAG EMPH EFMOUT DIVN[0] DAC_BCK BCKO BCKO
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PRELIMINARY
S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
$B0 Command Serial aduio data interface control
Data Command SADT I/F control Address D7 10100000 ($B0) D6 D5 D4 D3 D2 D1 D0 MSON
MSON: Serial audio data interfce on/off (ESP on/off) H: On L: Off
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PRELIMINARY
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
$F0 Command Data processing speed control
Data Command Play mode control Address D7 11110000 ($A9) DS1 D6 DS0 D5 D4 D3 D2 DFCK D1 D0 -
DS1, DS0:
X1, X2 speed control DS1 0 1 DS0 0 1 Mode 1X 2X
DFCK 1-bit DAC speed control H: 2X L: 1X
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PRELIMINARY
S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
EFM DEMODULATION EMF block is a circuit, which demodulates the EMF signal read from the disc, and is composed of the frame sync detection circuit and the control signal generator circuit. EFM Demodulation When the modulated 14 channel bit data is input, they are demodulated to 8 bit data. The demodulated data are classified into two types, the subcode data and audio data. The subcode data is input to the subcode processing block and the audio data is stored in the internal SRAM, after which it is corrected for error. Frame Sync Detection/Protection/Insertion Frame sync detection The data is configured in the unit of frames, of which frame sync, subcode data, audio data, redundancy data are configured in one frame. The frame sync is detected because it is used as the reference signal to synchronize the data output from the frame sync for extracting correct data. (Related Command Register: $92, FSMD [1:0]) Frame sync protection/insertion Frame sync may be detected in data besides that of frame sync or omitted due to effects from disc defects or jitters etc. In such cases, frame sync must be protected and inserted. A window must be made according to the $92 command register's WSEL[1:0] to protect frame sync. The data that enter this frame syn is the valid data and the frame sync that exits this window is ignored. If frame sync is not detected in the frame sync protection window, the frame sync made in the internal counter is inserted. If frame sync is inserted continuously to reach the number of frames specified by FSEL[1:0] of the $92 command register, the frame sync protection window is ignored as ULKFS becomes 'H' and the following frame sync detected is immediately accepted. If the frame sync is accepted, ULKFS signal becomes "L" to accept the frame sync detected in the window.
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DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
SUBCODE The subcode sync signal SOS1 is detected in the subcode sync block. After SO is detected, S1 is detected after one frame passes. At this time, SO+S1 signal is output through the SOS1 terminal, and SOS1 signal is output through the SBDT terminal when the SOS1 signal is ' H'. Of the data input to the EFMI terminal, 14-bit subcode data is EFM demodulated, synchronized with the WFCK signal to become 8-bit (P, Q, R, S, T, U, V, W) subcode data and output as SBDT through the SBCK clock. Of the 8 subcode data, only Q data is selected and saved in 80 shift registers using the WFCK signal. The CRC results of the stored data are synchronized to the S0S1 positive edge and output through the SQOK. If the CRC results are error, 'L' is output to the SQOK terminal and, if not, 'H' is output. If CRCQ's $93 command register is 'H', CRC results are output through the SQDT terminal from the interval that SOS1 is 'H' to the negative edge of SQCK. The following illustrates the timing diagram of the subcode block. SQCK, SQDT, S0S1 Timing Relationship
SOS1 SQOK SQCK
~ ~ ~ ~ ~ ~ ~ ~
SQDT (CRCQ=1) SQDT (CRCQ=0)
SQOK(n) Q4 0 Q4 Q3 Q3 Q2 Q2 Q1 Q1 Q8 Q8 Q7 Q7 Q6 Q6 Q5 Q5
SQOK(n+1) Q80 Q79 Q78 Q80 Q79 Q78 Q77 Q77 0 Q4 Q4 Q3 Q3
NOTE: If CRCQ of the subcode-Q data is 'H', SQOK signal is output through SQDT according to the SQCK signal and, if CRCQ is 'L', SQOK signal is not output through SQDT.
~ ~ ~ ~ ~ ~ ~ ~
SBDT, SBCK Timing Relationship
WFCK i SBCK SBDT ii Q R S T U V W iii 1 2 3 4 5 6 7 8
i. ii.
SBCK is set to 'L' for approximately 10us after WFCK becomes negative edge. If SOS1 is 'L', subcode P is output but , if SOS1 is 'H', SOS1 is output.
iii. If more than 7 pulses are input to the SBCK terminal, subcode data P, Q, R, S, T, U, V, W data are output repeatedly.
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PRELIMINARY
S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
ECC (ERROR CORRECTION CODE) If the data on the disc is damaged, the ECC (Error Correction Code) block is used to correct data. The CIRC (Cross Interleaved Reed-Solomon Code) is used to correct to 2 errors for C1 (32, 28) and 4 erasures for C2 (28, 24). For error correction, the data is processed in 1 symbol of 8-bit. Furthermore, the ECC block has the pointer function which generates the C1 pointer for C1 correction and C2 pointer for C2 correction. C1 and C2 pointers output flags for ECC processed data to indicate that the data has error. This flag signal is input to the block and used to process the error data. The error correction results can be monitored through MNT3-MNTO terminals. (Related Command Register: $A9, TALK[2:0])
Mode C10 error C11 error C12 error C1 correction impossible C20 error C21 error C22 error C23 error C24 error C2 correction impossible 1 C2 correction impossible 2 INTERPOLATION
MNT3 ECFL3 0 0 0 1 0 0 0 0 1 1 1
MNT2 ECFL2 0 0 1 0 0 0 1 1 0 0 1
MNT1 ECFL1 0 1 0 0 0 1 0 1 0 1 0
MNT0 ECFL0 0 0 0 0 1 1 1 1 1 1
Comment C1 flag = reset C1 flag = reset C1 flag = set/reset C1 flag = set C2 flag = reset C2 flag = reset C2 flag = reset C2 flag = reset C2 flag = reset C2 flag = set Copy C1 flag
When a burst error is generated on the disc, there are cases when the data cannot be corrected even with the ECC process. The interpolator block uses the ECC'S C2 pointer to interpolate the data. The audio data is input for L/Rch in 8-bit C2 point, lower data 8-bit, and upper data 8-bit order, respectively, to the data bus. If C2PO terminal is 'H' and there is only one error, the average value is interpolated, but, if there are 3 continuous errors, all values are hold interpolated. If LRCK is 'L' for one LRCK cycle, R-ch data is output, and, if 'H', L-ch is output. The timing clock in the interpolator block is shown below.
A
B
C D E F G
H
I
J
C2 Pointer B: Average value interpolation F = E = D: All value hold interpolation G: Average value interpolation
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PRELIMINARY
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
SERIAL AUDIO DATA INTERFACE Converts the 16-bit parallel data sent by the interpolation block to serial data. S5L9290X supports the following serial audio data format. The LRCK frequency for 1X is 44.1kHz and 2X is 88.3kHz.
Fs = 44.1/88.2kHz LRCHO 12 BCKO SADTO R-CH (MSB) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L-CH (MSB) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 24 25 48 1
MUTE & ATTENUATION The mute signal can be accepted in two ways. * * When mute port (pin #: 44) is "H" When $91 command register's D7 bit is "H"
The audio data is either muted or reduced based on the mute signal and ATTN signal of the $91 command register. Zero Cross Mute After ZCMT of the $91 command register is set to 'H', and the mute signal becomes 'H', and the audio data top 6bit all are either 'L' or 'H', the audio data is muted. Mute When ZCMT of $91 command register is 'L' and the mute signal becomes 'H', the audio data is muted. Attenuation The signal is reduced by the ATTN of $91 command register and mute signals. ATTN 0 0 1 1 Digital Attenuation By referencing command register $5D, 26 = 64 attenuation levels can be controlled. When the reset signal becomes 'L', the attenuation level is initialized to 0dB.
Dattn Gain = 20 x log ---------------64
MUTE 0 1 0 1
Degree of Attenuation [dB] 0 - -12 -12
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PRELIMINARY
S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
Soft Mute When the digital attenuation level is controlled from 0dB to -dB, the soft mute function can be configured. DAC Mute When the $91 command register's DAC_MUTE is "H", only the DAC block is muted. DIGITAL AUDIO OUT This digital audio out block outputs 2-channel and 16-bit data to another digital set in serial format based on the digital audio interface format. The advantage of this interface method is that communication is possible with only one pin, that is, additions such as a separate clock are not required. CD digital audio interface format
X
Channel 1
Y
Channel 2
Z
Channel 1
Y
Channel 2
X
Channel 1
Y
Channel 2
SubFrame 1 Frame 191
SubFrame 2 Frame 1
Frame 0 Start of Block
1. 1 block = 192 frame 2. 1 frame = 2 subframe 3. Frame 0, channel 1 - Block sync preamble, Z included Ch.1 format 4. Frame 1, channel 1-frame 191, channel 1 - Ch.1 sync preamble, X included Ch.1 format Frame 0, channel 2-frame 191, channel 2 - Ch.2 sync preamble, Y included Ch.2 format
0 34 78 Preamble AUX LSB Preamble AUX Data Audio Data Valid Data User Data Channel Data Parity Data
Audio Data
MSB
27 28 29 30 31 VUCP
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DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
Digital Audio Interface Timing Chart Each subframe is composed of 32 time slots, and audio data is included in the subframe. Two subframes make one frame, which has both left and right stereo signal components; 192 frames make one block, which is in the control bit data unit.
fs = 44.1kHz 128fs
bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7
...
bit n bit24 bit25 bit26 bit27 bit28 bit29 bit30 bit31
Digital Audio Out Source Coding Channel Coding (Biphase Mark) Preamble Z
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S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
SUBFRAME FORMAT Preamble (4 bits): The preamble has each subframe and block sync data. The preamble is not converted to biphase signal to maintain the inherent characteristic of the sync. On the other hand, it starts with the values opposite the phase 1 values of all the. The preamble requires three patterns, that is, a pattern to distinguish between and right and patterns that indicate start of the block. These patterns are shown.
Preceding State
0 Channel Coding
1
"X" "Y" "Z"
11100010 11100100 11101000
00011101 00011011 00010111
Subframe 1 Subframe 2 Subframe 1 and block start
Preamble 'X' is the channel 1 sync; preamble 'Y' is the channel 2 sync; and preamble 3 is to show the start sync of the block. The reason that there are 2 sync patterns for preamble is that the value reverses according to the phase of the previous data. AUX (4 bits): Auxiliary data area. Audio data (20 bits): Although the audio data resolution for the CD transmitted to digital out is usually 16 bits, it can also be transmitted as 20 bits or 24 when AUX is to be included. This area is LSB first. Validity bit (1 bit): If the audio sample word can be converted to analog audio signal, the validity bit to '1' and, if not, to '0'. For the CD, set it to '0'. User data (1 bit): This domain is used to transmit the subcode data for CD. Control status data (1 bit): Data is input for each subframe, and 192 subframes must be gathered to make one control data. This domain has both the consumer mode and professional mode, of which S5L9288X the consumer mode. The control status data for CD has the following meaning. Parity data (1 bit): Use even parity
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DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
Bit 0 1 2 3 4 5 6-7
Control Status Data 0 : Consumer use 1 : Professional use 0 : Normal audio mode 1 : Non-audio mode 0 : Copy prohibit 1 : Copy permit 0 : No pre-emphasis 1 : Pre-emphasis Reserved 0 : 2-channel 1 : 4-channel Mode 00 : mode 0 other : Reserved Category code 10000000 : 2-channel CD player Source number Channel number Sampling rate 0000 : 44.1kHz 0100 : 48kHz 1100 : 32kHz other : reserved Clock Accuracy 00 : Normal accuracy 10 : High accuracy 01 : Variable speed Don' care t
Default Value 0 0 0/1 0/1 0 0 00
8 - 15 16 - 19 20 - 23 24 - 27
10000000 0000 0000 -
28 - 29
-
30 - 191
all zero
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S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
SIGMA-DELTA STEREO DAC As a digital-to-analog converter that uses the modulation, the DAC installed in S5L9290X is composed of the digital attenuation, de-emphasis filter, FIR filter, SINC filter, digital sigma-delta modulator, analog post-filter, antiImage filter etc. Normal input/output characteristics exist at 20kHz. It has SNR (Signal to Noise Ratio) above 90dB. Timing Chart
Fs = 32/44.1/48kHz LRCHI 12 BCKI SADTI R-CH (MSB) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L-CH (MSB) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 24 25 48 1
32/44.1/48kHz Sampling Frequency (Fs) Support If the DAC master clock is applied to 384 x Fs cycle, it supports 3 sampling frequencies. If the command register $94's MSCKSW is "H" and command register $A9's RFCK_OEN is "L", the external master clock can be applied to the RFCK terminal. X1, X2 Speed Support If the command register $93's DFCK is set to "H", the internal data input rate becomes 2*Fs and the speed becomes 2X. Application Circuit
39 VDDD_DAC
34 VDDA_DAC
1uF 0.1uF10uF 0.1uF10uF 0.1uF10uF 100K
1uF 0.1uF10uF 100K
Lch
Rch
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40 VSSD_DAC
37 VAAS_DAC
38 RCHOUT
33 LCHOUT
35 VHALF
36 VREF
PRELIMINARY
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
DIGITAL CLV SERVO This block controls the spindle motor speed by using RFCK and WFCK data to generate the control .Digital CLV Servo control related Command Registers are $93, $94, and $98 $9E. Forward (Kick) Mode Mode ($99) that rotates the spindle motor in forward direction. SMDP H Reverse (Brake) Mode Mode ($99) that rotates the spindle motor in the reverse direction. SMDP L Stop Mode Mode ($99) that stops the spindle motor. SMDP L Speed (CLV-S) Mode ($99) Controls the spindle motor during a track jump or if the EFM phase is unlocked. Although the pulse width of the frame sync signal detected from the EFM signal is exactly 22T in PLCK cycle (T), it can be greater or less than 22T depending on the player status. WB and WP of the command register $98 are used to control the frame sync detection cycle. SMDP L : deceleration H : acceleration Hi-Z : remain SMDS Hi-Z SMEF L SMON H SMDS Hi-Z SMEF L SMON L SMDS Hi-Z SMEF L SMON H SMDS Hi-Z SMEF L SMON H
Detected Frame Sync Pulse Width 21T = 22T 23T
SMDP L (deceleration) Hi-Z (remain) H (acceleration)
Comment If the command Register $98's GAIN is 'L', the SMDP output is output after it has been attentuated by -12dB, but if 'H', it is output without being attentuated.
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S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
P22T N22T SMDP deceleration under 22 t acceleration over 22 t
= 22 t
Phase (CLV-P) Mode (Command Register : $99) As the EFM signal phase control mode, this mode precisely controls the spindle motor rotation speed. Two methods of control are Phase control and Frequency control and the two signals produced, are sent to the SMDP and SMDS, respectively. NCLV of the command register $93 can be used to change the reference clock, which is used in phase control. The phase control signal is sent to SMDP and its waveform is shown below.
Phase Error Signal
RFCK/4 WFCK/4 DOWN UP SMDP
If the system clock and C4M cycles are T and WFCK's width, 'H', is tHW, SMDS outputs 'H' starting from WFCK's negative edge for (tHW - rise_mtval) x SGAIN and then falls to 'L'. Here, the rise_mtval and SGAIN values can be set through command register $9B.
tHW = 288T WFCK tHW = 288T SMDS
tHW = 294T (THW-279T)*32 = 480T
< SMDS output waveform in Phase (CLV-P) Mode: SGAIN = 32, rise_mtval = 279 >
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DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
XPHSP (CLV-A) Mode (Command Register : $99) In this normal operation mode, the speed mode and phase mode are change alternately by the lock signal. After the LKFS signal generated by the frame sync block is sampled in WFCK/16 cycles and is detected to be 'H', the phase mode executes and, if it is detected as 'L' eight consecutive times, the speed mode automatically executes. LOCK generation If the LKFS signal remains at 'L' for the frame time, provided by Micom Command $99's UNLOCK[1:0], or for less, LOCK remains at 'H'. However, if it remains at 'L' for more than the given frame, the LOCK changes to 'L'. The time in LOCK is the same for 1X and 2X speed. Additional Functions ($9B's POS must be set to = 'H') 1) SMDS masking This function prevents sensitive CLV servo response to small frequency error changes. If the SME of $9A is set to 'H', it operates in the SMDS masking mode (dead zone enable). The SML[1:0] masking range of $9B is set, and, if $9A's SMM bit is 'H', SML value becomes the absolute value of the masking range, set by 9D'h SMOFFSET[3:0], but if 'L', then the value is set to the one shown in the table below. If SMDS frequency error, that is, WFCK high width is within the masking range, the SMDS output is PWM of 50:50 or Hi-Z is output. (Determined by $9A's STRIO) If SMDS masking occurs, SMDP output is masked automatically and Hi-Z is output. Command order : $9B(SML) $9D(SMOFFSET) $9A (SME, SMM)
SML[1:0] 00 01 10 11
masking error range (SML = 'L') 0 % 6.25 % 12.5 % 25 % < SML[1:0] setting >
SMDS High width (t)
288t WFCK WFCK High width (t) 1t = 1/8.4672MHz
288t masking error area (deas zone area) Maximum error area
< Dead Zone Area >
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PRELIMINARY
S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
SMDP masking When the SMDS masking is enabled, the SMDP output is automatically masked in the dead zone area. There are two modes for masking only the SMDP without masking the SMDS. In the first mode, if $9A's SME is set to 'L' and PME is set to 'H', the SMDP masking mode operates. At this time, if the phase error is greater than 50% or 25% of the WFCK frequency error (determined by $9B's PML), SMDP output is masked. That is, the output is Hi-Z. This is to reduce the phase error effect at the state in which the frequency error is not sufficiently small. In the second mode, after setting SME and PME of $9A, PCEN of $99 can be used to set SMDP masking. In this case, if PCEN of $99 is set to 'H' and WFCK frequency error enters the dead zone area set by SML, the SMDP output is maked to Hi-Z. Command order : $9B(PML) $9A(PME), $9B(SML) $99(PCEN) CLV emergency mode (ECLV) When there are events such as a focus drop, an unstable EFM is input and this in turn causes the spindle motor to overload. To prevent such an overload, the Micom notifies the CLV servo of such emergency conditions, and then CLV servo outputs H, Hi-Z and L repeatedly in regular intervals. This is all executed by the micom, which sets the ECLV of $93 to 'H' and changes the CLV mode to CLV-S mode. Then, SMDS outputs Hi-Z and SMDP outputs H, Hi-Z and L repeatedly in an interval determined by ECLV_PD of $93. ECLV_PD 1 0 Comment bottom hold pulse interval peak hold pulse interval
Command order : $93(ECLV, ECLV_PD) $99(CM3,CM2,CM1,CM0) Defect response mode If the EFM enters as'L' for a specific time due to a Scratch or defect, there is no PLL control, which fixes the PLCK to any frequency; this in turn fixes the WFCK and consequently the CLV servo output is fixed in the direction of acceleration or deceleration. In such a case, the final CLV speed can be reduced when normal EFM re-enters. If CLV_DFCT of $A2 is set to 'H', the CLV servo outputs, SMDP and SMDS, can be output as Hi-Z and 50:50, when EFM width is greater than 64t to prevent deceleration or acceleration. Oversampling output The SMDS output frequency is 7.35kHz at 1X speed and 14.7kHz at 2X speed. These are within the audio frequency range, so they be used as normal audio output noise source. Therefore, OVSPL of $98 can be set to 'H' and SMDS and SMDP frequencies can be oversampled by four times at 7.35KHz * 4 = 29.4kHz and output. If OVSPLMD of $98 is set to 'H', the SMDS becomes tri-state t output and, if set to 'L', SMDS become a PWM output. CLV IDLE mode This mode rotates the spindle motor at a fixed rate regardless of the EFM input. To operate in the CLV IDLE mode, the $9E's SOFFSET[7:0] value, which represents the SMDS high width, must be set. Furthermore, if $99's CLV_IDLE is set to 'H', the SMDP output becomes Hi-Z, and SMDS outputs High for the duration of SOFFSET set value * 118ns in one cycle and outputs Hi-Z in the remaining intervals.
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PRELIMINARY
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
SMDS SOFFSET
Hi-Z
< SMDS output > SMDS gain control If the pickup or spindle motor is changed, the entire CLV loop transfer function changes and thus CLV gain must be controlled. The CLV servo is changed to PI controller type; we can assume that the frequency error output SMDS controls the P gain and the phase error output SMDP controls the I gain. SMDS gain can be set to 9B'h SGAIN[2:0] , where gain values of SGAIN are shown below. In terms of a graph, the gain is the slope.
SGAIN[2:0] 000 001 010 011 100 101 110 111
Gain Value 1 2 4 8 16 32 64 128 < SMDS gain setting >
rise_mtval 0 144 216 252 270 279 283 285
SMDS High width (t)
288t WFCK High width (t) 1t = 1/8.4672MHz 288t Maximum error area
rise_mtval
< SMDS gain vs SMDS output >
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PRELIMINARY
S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
There is an additional feature which allows the addition of an offset to WFCK frequency error for output. If $9D's SPLUS is set to 'H' and $9E's SOFFSET[7:0] is set, the SOFFSET value is added to the frequency error, and the product of this value and the gain is output to SMDS. SMDP gain control The 9B'h POS must be set to 'H' for SMDP gain control. Furthermore, SMDP gain must be set to $9A's PGAIN[1:0]. The clock resolution, which measures WFCK and RFCK's phase error, must be set to $9A's PKSEL.
PGAIN[1:0] 00 01 10 11
gain 1 1/2 1/4 2
PKSEL[1:0] 00 01 10 11 frequency clk4M/2 clk4M/4 clk4M/8 clk4M/16
< Phase error resolution clock setting > If POFFSET[7] is 'H', the value is subtracted and, if 'L', added. . SMDS output Mode If $9A's STRIO is set to 'H', the SMDS is output in tri-state (H, Hi-Z, L) states in phase mode. If $9D's SDD is set to 'H', the SMDS outputs as Hi-Z in phase mode if the WFCK frequency error is a deceleration error. Even if SMDS is output as Hi-Z, this mode can reduce the power consumption by utilizing the principle of deceleration due to motor friction.
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PRELIMINARY
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L9290X
DIGITAL PLL Essentially uses the existing digital PLL configuration while changing the frequency of the frequency synthesizer, which suppliew the DPLL clock, according to the EFM signal bit rate to allow wide capture range PLL. Wide capture range PLL is generated the SRAM jitter by changeing the in/output rate of SRAM buffer and can selected the jitterfree mode to prevent the SRAM jitter.
PLL1 XIN
PHASE DETECTOR1
1/P1
DPDO1
LOOP FILTER1 CNTVOL1
1/M1 VCO1O
VCO1
1/S1
M1 FREQUENCY DETECTOR
EFMI
DPLL
PLCK
to EFM demodulation
< Block Diagram > PLL1 is the frequency synthesizer to supply the reference clock in DPLL and receives the crystal input (16.9344MHz) to generate a clock with Xtimes of PLCK. The next is frequency equation of frequency synthesizer and is changed the divider value automally by sekect the times
m Font = Fin x -----------pxs
Fin: input frequency, Font: output frequecy p: ore-divider (=DIVP+2), m: main-divider (DIVM+8), s: port-scalor (2DIVS)
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PRELIMINARY
S5L9290X
DIGITAL SIGNAL PROCESSOR FOR CDP
PACKAGE DIMENSION
9.00 + 0.30 0-7 7.00 + 0.20 0.125
+ 0.073 - 0.037
9.00 + 0.30
7.00 + 0.10
0.08 MAX
#48
#1 0.50
0.20
+ 0.07 - 0.03
0.05 MIN (0.75) 1.40 + 0.05 1.60 MAX
0.08 MAX
NOTE: Dimensions are in millimeters.
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0.45 - 0.75

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